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n2206 / o2505 ms ot b8-8873 no.a0015-1/16 LA72700V overview LA72700V is a us mts (multi channel television sound) decoder. features ? with sif circuit, stereo chan nel separation is alignment-free. ? built-in filters are adjustment free. ? sap output level is selectable 2 levels. ? included control function for stereo and sap detection sensitivity. functions ? sif fm-demodulator. ? stereo decoder. ? alc function is included. ? dbx noise reduction system. ? sap demodulator. ? stereo detection. ? sap detection. specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum power supply voltage v cc max 9.6 v allowable power dissipation pd max ta 70 c * 810 mw operating temperature topr -10 to +70 c storage temperature tstg -55 to +150 c * on board (114.3 76.1 1.6 mm glass epoxy resin board) ordering number : ena0015 monolithic linear ic us mts (multi channel television sound) decoder any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein.
LA72700V no.a0015-2/16 operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended operating voltage v cc 9.0 v operating voltage range v cc op 8.5 to 9.5 v electrical characteristics at ta = 25 c, v cc = 9.0v ratings parameter symbol conditions min typ max unit current dissipation i cc no signal inflow current at pin 31 * default condition 50 60 70 ma sif input level (reference) vilim fc = 4.5mhz deviation mono (300hz, mod = 100%, pre-emphasis on) ? 25khz (80) (90) (100) db v base band input level (reference) vilimb 100% modulation mono(l+r): 530mvp-p (300hz, pre-emphasis on) sub(l-r): 380mvp-p (300hz, dbx-nr on), pilot: 110mvp-p sap: 300mvp-p (300hz, dbx-nr on) mono output level vomon input: fm = 1khz, 100% mod, monoral measure out (l), out (r) -7.0 -6.0 -5.0 dbv mono distortion thdmon input: fm = 1khz, 100% mod, monoral measure out (l), out (r) 0.15 0.6 % mono frequency characterist ics fcm1 input: fm = 8khz, 30% mod, monoral measure out(l), out(r), ratio from fm = 1khz level. -2 0 2 db mono s/n ratio snm s = vomon, n = 0% mod measure out (l), out (r) with 15khz lpf, jis-a 55 65 db stereo output level vost input: fm = 1khz, 100% mod, stereo measure out (l), out(r) -7.0 -6.0 -5.0 dbv stereo distortion thds input: fm = 1khz, 100% mod, stereo measure out (l), out (r) 1.0 2.5 % stereo frequency characteristics fcs1 fm = 8khz, 30% mod, stereo measure out (l), out (r), ratio from fm = 1khz level. -3 0 3 db stereo s/n ratio sns s = vost, n = 0% mod measure out (l), out (r) with 15khz lpf, jis-a 50 60 db stereo separation 1 stse1 f = 300hz (r/l), 30% mod measure ratio out (l) with out (r) 20 25 db stereo separation 2 stse2 f = 3khz (r/l), 30% mod measure ratio out (l) with out (r) 20 25 db stereo detection level-1 vinsd1 except stereo detection ? stereo detection measure pilot level, at stero det. 52 57 62 % stereo detection level-2 vinsd2 except stereo detection ? stereo detection * insert resistor pin 14 to gnd (ex. 51k ? ) measure pilot level, at stero det. 62 67 72 % continued on next page.
LA72700V no.a0015-3/16 continued from preceding page. ratings parameter symbol conditions min typ max unit stereo detection hysteresis hyst input mod. difference at stereo /except stereo det. * at default condition 10 15 25 % sap output level-1 vosa fm = 1khz, 100% mod, sap measure out (l), out * at bit6 = 0 -7.5 -6.5 -5.5 dbv sap output level-2 vosa2 fm = 1khz, 100% mod, sap measure out (l), out * at bit6 = 1 -5.5 -4.5 -3.5 dbv sap distortion thdsa fm = 1khz, 100% mod, sap measure out (l), out 1.5 3.5 % sap s/n ratio snsa s = vosa, n = 0% mod, measure out (l), out (r) with 15khz lpf, jis-a 55 65 db sap detection level-1 vinsa1 measure sap carrier level, when sap det * default condition 13 18 23 % sap detection level-2 (reference) vinsa2 measure sap carrier level, when sap det * pin15 to gnd (ex 33k ? ) (5) (10) (15) % sap detection level-3 (reference) vinsa3 measure sap carrier level, when sap det * pin15 to gnd (ex 8.2k ? ) (20) (25) (30) % sap detection hysteresis hysa input mod. difference at sap/except sap det. * at default condition 2 5 10 % mode output mono modmo input = mono: f = 1khz, 0% mod measure pin32 0.7 1 1.3 v mode output sap modsa input = sap: carrier measure pin32 1.7 2 2.3 v mode output stereo modst input = stereo: pilot measure pin32 2.7 3 3.3 v mode output st + sap mod ss input = stereo: pilot, sap: carrier measure pin32 3.5 3.8 4.2 v distortion thdalc mono 1khz mod 100% * alc on measure out (l), out (r) 0.3 0.5 % * normally measurement condition is input = sif mode (-90dbv), alc = off * " reference " items are reference levels, their specs are no-guarantee. package dimensions unit : mm 3247b
LA72700V no.a0015-4/16 block diagram and application circuit example
LA72700V no.a0015-5/16 00p-1 ( normally use : group-1 only ) d8 d7 d6 d5 d4 d3 d2 d1 condition * 0 0 stereo 0 1 sap 1 0 both 1 1 prohibit * 0 normal (auto det) 1 forced mono * 0 normal (mute off) 1 mute * 0 alc off (through) 1 alc on * 0 sap level-1 1 sap level-2 * 0 sif mode 1 base band mode * 0 fix 1 prohibit (test mode) *: initial condition read out data d8 d7 d6 d5 d4 d3 d2 d1 condition 0 0 0 0 0 0 fixed 0 normal 1 sap det 0 normal 1 stereo det test mode condition when stop condition transform at grp-1 data-end, controlled normal mode. grp-2(only test condition: normally, this data is no-need) d8 d7 d6 d5 d4 d3 d2 d1 condition/monitor position 0 0 0 0 0 0 0 0 normal (usually, fixed) 0 0 0 0 0 0 0 1 test-1 sif output 0 0 0 0 0 0 1 0 test-2 sap bpf 0 0 0 0 0 0 1 1 test-3 sap vco 0 0 0 0 0 1 0 0 test-4 st vco 0 0 0 0 0 1 0 1 test-5 adj vco 0 0 0 0 0 1 1 0 test-6 dbx input 0 0 0 0 0 1 1 1 test-7 l-r demod output 0 0 0 0 1 0 0 0 test-8 pilot cancel 0 0 0 0 1 0 0 1 test-9 dbx 2.19k lpf 0 0 0 0 1 0 1 0 test-10 dbx 408 lpf 0 0 0 0 1 0 1 1 test-11 dbx det 10k lpf 0 0 0 0 1 1 0 0 test-12 dbx spec 7.6k lpf 0 0 0 0 1 1 0 1 test-13 dbx spec output 0 0 0 0 1 1 1 0 test-14 (no operation) 0 0 0 0 1 1 1 1 test-15 (no operation)
LA72700V no.a0015-6/16 pin functions dc voltage no. pin function ac level input/output form reference 1 pc_dc_in dc: 3.8v ac: 2.4vp-p ac coupling (input) 2 pc_dcout dc: 3.8v ac: 2.4vp-p ac coupling (output) 3 pcstfilt dc: 3.8v stereo vco pll filter 4 pcpldet dc: 3.8v pilot level detect 5 pisif dc: 3.7v signal input continued on next page.
LA72700V no.a0015-7/16 continued from preceding page. dc voltage no. pin function ac level input/output form reference 6 gnd csapdet dc: 2.8v sap carrier level detect 8 nc no connect 9 pc fil dc: 2.9v sif offset cancel 10 mute dc: 0v mute = 5v 11 sda serial data input 12 scl serial clock input continued on next page.
LA72700V no.a0015-8/16 continued from preceding page. dc voltage no. pin function ac level input/output form reference 13 pc dbxin dc: 2.5v offset cancel filter 14 pstsens dc: 3.1v stereo det sensitivity change open = default insert resistor(30k or over) = low sensitivity 15 psapsens dc: 3.1v sap detect sensitivity control open = default controlled by insert resistor * see electrical reference 16 pctnwid dc: 4.0v dbx rms detect(wide band) 17 pcdetwid dc: 3.8v dbx wide detect continued on next page.
LA72700V no.a0015-9/16 continued from preceding page. dc voltage no. pin function ac level input/output form reference 18 pctimspe dc: 3.8v 5k ? 18 omp05019 dbx spectral detect 19 pcdetspe dc: 3.8v dbx rms detect (spectral band) 20 pcspecin dc: 3.8v dbx main signal v/i convert filter 21 pcdospe dc: 3.8v ac: 220mvp-p offset cancel filter 22 pcdbxout dc: 3.8v ac: 220mvp-p ac coupling (output) 23 pcdbx_in ac coupling (input) continued on next page.
LA72700V no.a0015-10/16 continued from preceding page. dc voltage no. pin function ac level input/output form reference 24 pcalcfil dc: 0.6v alc filter * when alc function no-use, this terminal is open. 25 porch dc: 3.8v ac: 1.4mvp-p line out r 26 polch dc: 3.8v ac: 1.4mvp-p line out l 27 pcreg dc: 3.8v reference voltage continued on next page.
LA72700V no.a0015-11/16 continued from preceding page. dc voltage no. pin function ac level input/output form reference 28 pmain_in dc: 3.5v ac: 220mvp-p ac coupling (input) 29 pmainout dc: 3.8v ac: 220mvp-p ac coupling (output) 30 pcreg76 dc: 1.2v regulator 31 v cc 32 poled dc* * see mode table mode out mono = 0.9v sap = 2.0v stereo = 3.0v stereo+sap = 3.8v 33 piclkfsc dc: 0v ac* * 200mvp-p recommend fsc input 3.579545mhz, 200mvp-p continued on next page.
LA72700V no.a0015-12/16 continued from preceding page. dc voltage no. pin function ac level input/output form reference 34 pcdjfil dc: 2.5v filter adjustment signal detect 35 pcplc dc: 6.3v pilot canceller reference-1 36 pcplc2 dc: 6.3v pilot canceller reference-2
LA72700V no.a0015-13/16 serial control (i 2 c) (1) data transfer manual this lsi adopts control method (i 2 c -bus) with serial data, and controlled by two terminals which called scl (serial clock) and sda (serial data). at first, set up *1 the condition of starting data transfer , and after that, input 8 bit data to sda terminal with synchronized scl terminal clock. the orde r of transferring is first, msb (the most scale of bit), and save the order. the 9th bit takes ack (acknowledge) period, during scl terminal takes ?h?, this lsi pull down the sda terminal. after transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition , thus the transfer comes to close. *1 defined by scl rise down sda during ?h? period. *2 defined by scl rise up sda during ?h? period. (2) transfer data format after transfer start co ndition, transfers slave address (1000000*) to sd a terminal, control data, then, stop condition (see figure 1). slave address is made up of 7bits, *3 8th bit shows the direction of transferring data, if it is ?l?, takes write mode (as this lsi side, this is input operation m ode), and in case of ?h?, reading mode (as this lsi side, this is output operation mode). data works with all of bit, transfer the stop condition before stop 8bit transfer, an d to stop transfer, it will be canceled the transfer dates. *3 it is called r/w bit. fig.1 data structure " write " mode start condition slave address r/w l ack control data ack stop condition fig.2 data structure " read " mode start condition slave address r/w h ack internal data * ack stop condition * output 5bits data as follows; bit8 is result of stero det (h: stereo) bit7 is result of sap det (h: sap) bit6 to bit1 are fixed to ?l?
LA72700V no.a0015-14/16 (3) initialize this lsi is initialized for circuit protec tion. initial condition is ?0 (all bits)?. parameter symbol min max unit low level input voltage v il -0.5 1.5 v high level input voltage vi ih 3.0 5.5 v low level output current i ol 3.0 ma scl clock frequency f scl 0 100 khz set-up time for a repeated start condition t su: sta 4.7 s hold time start condition. after this period, the first clock pulse is generated t hd: sta 4.0 s low period of the scl clock t low 4.7 s rise time of both sda and sdl signals t r 0 1.0 s high period of the scl clock t high 4.0 s fall time of both sda and sdl signals t f 0 1.0 s data hold time t hd: dat 0 s data set-up time t su: dat 250 ns set-up time for stop condition t su: sto 4.0 s bus free time between a stop and start condition t buf 4.7 s timing chart
LA72700V no.a0015-15/16 measurement circuit
LA72700V ps no.8340-16/16 specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of october , 2005. specifications and information herein are subjec t to change without notice.

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